`include "../../src/ALUcontrol.v"
`timescale 1ps/1ps

module testbench;
    reg clk;
    initial clk = 1;
    always #5 clk = ~clk;

    reg reset;
    initial reset = 0;

    reg[1:0] ALUop;
    reg[31:25] funct7;
    reg[14:12] funct3;
    wire[3:0] out; 

    initial
    begin
        ALUop = 2'b00;
        #10 ALUop = 2'b01;
        #10 
            ALUop = 2'b10;
            funct7 = 7'b0000000;
            funct3 = 3'b000;
        #10
            ALUop = 2'b10;
            funct7 = 7'b0100000;
            funct3 = 3'b000;
        #10 
            ALUop = 2'b10;
            funct7 = 7'b0000000;
            funct3 = 3'b111;
        #10 
            ALUop = 2'b10;
            funct7 = 7'b0000000;
            funct3 = 3'b110;
        #10
            ALUop = 2'b11;
        #10
            ALUop = 2'b10;
            funct7 = 7'b0000000;
            funct3 = 3'b010;
        #10 $stop;
    end

    ALUcontrol U0(clk, reset, ALUop, funct7, funct3, out);

    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end


endmodule